Intel 8080
Adapted from Wikipedia Β· Discoverer experience
The Intel 8080 was Intel's second 8-bit microprocessor, introduced in April 1974. It built upon the earlier Intel 8008 and became much more powerful and easier to use. The 8080 was first made for special jobs like calculators, cash registers, and computer terminals, but it soon became popular for many other uses, helping start the microcomputer industry.
Several smart design choices made the 8080 a big success. It had a simpler 40-pin package, worked faster with new technology, and could handle more memory than its predecessor. These changes came from ideas and feedback from people who used the earlier chip.
The 8080 was used in early personal computers like the Altair 8800 and helped create the x86 architecture that many computers still use today. It could run at 2 MHz and perform many tasks quickly, making it a key part of the first home computers.
History
The Intel 8080 was made to fix problems with an earlier chip called the 8008. People wanted a better chip, so Intel began working on the 8080 in 1971. The designers wanted to make a chip that could do more things and work faster.
The 8080 was finished in 1973 and officially released in April 1974. It became popular because it was better and faster than older chips. This chip helped start the era of small computers that many people could use.
Description
Programming model
The Intel 8080 is the successor to the Intel 8008. It uses the same basic instruction set and register model as the 8008, although it is neither source code compatible nor binary code compatible with its predecessor. Every instruction in the 8008 has an equivalent instruction in the 8080. The 8080 also adds 16-bit operations in its instruction set. The 8080 has addressing modes to directly access its full 16-bit memory space, unlike the 8008. The 8080's 40-pin DIP packaging provides a 16-bit address bus and an 8-bit data bus that access 64Β KiB (216 bytes) of memory.
Registers
The processor has seven 8-bit registers (A, B, C, D, E, H, and L), where A is the primary 8-bit accumulator. The other six registers can be used as individual 8-bit registers or in three 16-bit register pairs (BC, DE, and HL). The 8080 has a 16-bit stack pointer to memory, replacing the 8008's internal stack, and a 16-bit program counter.
Flags
The processor maintains internal flag bits (a status register), which indicate the results of arithmetic and logical instructions. The flags are:
- Sign (S), set if the result is negative.
- Zero (Z), set if the result is zero.
- Parity (P), set if the number of 1 bits in the result is even.
- Carry (C), set if the last addition operation resulted in a carry or if the last subtraction operation required a borrow.
- Auxiliary carry (AC or H), used for binary-coded decimal arithmetic (BCD).
Commands, instructions
As with many other 8-bit processors, all instructions are encoded in one byte, with some followed by one or two bytes of data. It has automatic CALL and RET instructions for multi-level procedure calls and returns and instructions to save and restore any 16-bit register pair on the machine stack. Eight one-byte call instructions (RST) for subroutines exist at fixed addresses. The slowest instruction is XTHL, which exchanges the register pair HL with the last item pushed on the stack.
8-bit instructions
All 8-bit ALU operations with two operands can only be performed on the 8-bit accumulator (the A register). Increments and decrements can be performed on any 8 bit register or an HL-addressed memory byte. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory byte.
16-bit operations
Although the 8080 is generally an 8-bit processor, it has limited abilities to perform 16-bit operations. Any of the three 16-bit register pairs (BC, DE, or HL) or SP can be loaded with an immediate 16-bit value, incremented or decremented, or added to HL. The only 16-bit instructions that affect any flag is DAD, which sets the CY (carry) flag. BC, DE, HL, or PSW can be copied to and from the stack using PUSH and POP.
Instruction set
See also: Intel 8008 Β§Β Instruction set, and Intel 8085 Β§Β Instruction set
Input/output scheme
Input output port space
The 8080 supports 256 input/output (I/O) ports, accessed via dedicated I/O instructions taking port addresses as operands. This I/O mapping scheme frees up the processor's limited address space. Many CPU architectures use memory-mapped I/O (MMIO), which uses a common address space for both RAM and peripheral chips.
Separate stack space
One of the bits in the processor state word indicates that the processor is accessing data from the stack. This feature is seldom used.
Status word
For more advanced systems, during the beginning of each machine cycle, the processor places an eight bit status word on the data bus. This byte contains flags that determine whether the memory or I/O port is accessed.
Interrupts
Hardware interrupts are initiated by asserting the interrupt request (INT) pin. Interrupts may be enabled and disabled with EI and DI instructions, respectively. Interrupts are disabled after an INTA; they must be re-enabled explicitly by the interrupt service routine. The 8080 does not support non-maskable interrupts.
Example code
The following 8080/8085 assembler source code is for a subroutine named memcpy that copies a block of data bytes of a given size from one location to another.
Pin use
The address bus has its own 16 pins, and the data bus has 8 pins. The processor needs three power sources (β5, +5, and +12Β V) and two non-overlapping high-amplitude synchronizing signals.
| Opcode | Operands | Mnemonic | Clocks | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | |||
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | β | β | NOP | 4 | No operation |
| 0 | 0 | RP | 0 | 0 | 0 | 1 | datlo | dathi | LXI rp,data | 10 | RP β data | |
| 0 | 0 | RP | 0 | 0 | 1 | 0 | β | β | STAX rp | 7 | (RP) β A [BC or DE only] | |
| 0 | 0 | RP | 0 | 0 | 1 | 1 | β | β | INX rp | 5 | RP β RP + 1 | |
| 0 | 0 | DDD | 1 | 0 | 0 | β | β | INR ddd | 5/10 | DDD β DDD + 1 | ||
| 0 | 0 | DDD | 1 | 0 | 1 | β | β | DCR ddd | 5/10 | DDD β DDD - 1 | ||
| 0 | 0 | DDD | 1 | 1 | 0 | data | β | MVI ddd,data | 7/10 | DDD β data | ||
| 0 | 0 | RP | 1 | 0 | 0 | 1 | β | β | DAD rp | 10 | HL β HL + RP | |
| 0 | 0 | RP | 1 | 0 | 1 | 0 | β | β | LDAX rp | 7 | A β (RP) [BC or DE only] | |
| 0 | 0 | RP | 1 | 0 | 1 | 1 | β | β | DCX rp | 5 | RP β RP - 1 | |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | β | β | RLC | 4 | A1-7 β A0-6; A0 β Cy β A7 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | β | β | RRC | 4 | A0-6 β A1-7; A7 β Cy β A0 |
| 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | β | β | RAL | 4 | A1-7 β A0-6; Cy β A7; A0 β Cy |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | β | β | RAR | 4 | A0-6 β A1-7; Cy β A0; A7 β Cy |
| 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | addlo | addhi | SHLD add | 16 | (add) β HL |
| 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | β | β | DAA | 4 | If A0-3 > 9 OR AC = 1 then A β A + 6; then if A4-7 > 9 OR Cy = 1 then A β A + 0x60 |
| 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | addlo | addhi | LHLD add | 16 | HL β (add) |
| 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | β | β | CMA | 4 | A β Β¬A |
| 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | addlo | addhi | STA add | 13 | (add) β A |
| 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | β | β | STC | 4 | Cy β 1 |
| 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | addlo | addhi | LDA add | 13 | A β (add) |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | β | β | CMC | 4 | Cy β Β¬Cy |
| 0 | 1 | DDD | SSS | β | β | MOV ddd,sss | 5/7 | DDD β SSS | ||||
| 0 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | β | β | HLT | 7 | Halt |
| 1 | 0 | ALU | SSS | β | β | ADD ADC SUB SBB ANA XRA ORA CMP sss | 4/7 | A β A [ALU operation] SSS | ||||
| 1 | 1 | CC | 0 | 0 | 0 | β | β | Rcc (RET conditional) | 5/11 | If cc true, PC β (SP), SP β SP + 2 | ||
| 1 | 1 | RP | 0 | 0 | 0 | 1 | β | β | POP rp | 10 | RP β (SP), SP β SP + 2 | |
| 1 | 1 | CC | 0 | 1 | 0 | addlo | addhi | Jcc add (JMP conditional) | 10 | If cc true, PC β add | ||
| 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | addlo | addhi | JMP add | 10 | PC β add |
| 1 | 1 | CC | 1 | 0 | 0 | addlo | addhi | Ccc add (CALL conditional) | 11/17 | If cc true, SP β SP - 2, (SP) β PC, PC β add | ||
| 1 | 1 | RP | 0 | 1 | 0 | 1 | β | β | PUSH rp | 11 | SP β SP - 2, (SP) β RP | |
| 1 | 1 | ALU | 1 | 1 | 0 | data | β | ADI ACI SUI SBI ANI XRI ORI CPI data | 7 | A β A [ALU operation] data | ||
| 1 | 1 | N | 1 | 1 | 1 | β | β | RST n | 11 | SP β SP - 2, (SP) β PC, PC β N x 8 | ||
| 1 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | β | β | RET | 10 | PC β (SP), SP β SP + 2 |
| 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | addlo | addhi | CALL add | 17 | SP β SP - 2, (SP) β PC, PC β add |
| 1 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | port | β | OUT port | 10 | Port β A |
| 1 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | port | β | IN port | 10 | A β Port |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | β | β | XTHL | 18 | HL β (SP) |
| 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | β | β | PCHL | 5 | PC β HL |
| 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | β | β | XCHG | 4 | HL β DE |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | β | β | DI | 4 | Disable interrupts |
| 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | β | β | SPHL | 5 | SP β HL |
| 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | β | β | EI | 4 | Enable interrupts |
| 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | b2 | b3 | Mnemonic | Clocks | Description |
| SSS DDD | 2 | 1 | 0 | CC | ALU | RP | ||||||
| B | 0 | 0 | 0 | NZ | ADD ADI (A β A + arg) | BC | ||||||
| C | 0 | 0 | 1 | Z | ADC ACI (A β A + arg + Cy) | DE | ||||||
| D | 0 | 1 | 0 | NC | SUB SUI (A β A - arg) | HL | ||||||
| E | 0 | 1 | 1 | C | SBB SBI (A β A - arg - Cy) | SP or PSW | ||||||
| H | 1 | 0 | 0 | PO | ANA ANI (A β A β§ arg) | |||||||
| L | 1 | 0 | 1 | PE | XRA XRI (A β A β» arg) | |||||||
| M | 1 | 1 | 0 | P | ORA ORI (A β A β¨ arg) | |||||||
| A | 1 | 1 | 1 | N | CMP CPI (A - arg) | |||||||
| SSS DDD | 2 | 1 | 0 | CC | ALU | |||||||
| Pin number | Signal | Type | Comment |
|---|---|---|---|
| 1 | A10 | Output | Address bus 10 |
| 2 | GND | β | Ground |
| 3 | D4 | Bidirectional | Bidirectional data bus. The processor also momentarily transmits the "processor state" during SYNC^Ο1, providing information about what the processor is currently doing: D0 (INTA) reading interrupt command. In response to the interrupt signal, the processor is reading and executing a single arbitrary command with this flag raised. Normally the supporting chips provide the subroutine call command (CALL or RST), transferring control to the interrupt handling code. D1 (WO-) low true. Write to memory or output to port D2 (STACK) accessing stack (probably a separate stack memory space was initially planned) D3 (HLTA) doing nothing, has been halted by the HLT instruction D4 (OUT) writing data to an output port D5 (M1) reading the first byte of an instruction D6 (IN) reading data from an input port D7 (MEMR) reading data from memory |
| 4 | D5 | ||
| 5 | D6 | ||
| 6 | D7 | ||
| 7 | D3 | ||
| 8 | D2 | ||
| 9 | D1 | ||
| 10 | D0 | ||
| 11 | β5 V | β | The β5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged. |
| 12 | RESET | Input | Reset. This active low signal forces execution of commands located at address 0000. The content of other processor registers is not modified. |
| 13 | HOLD | Input | Direct memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state. |
| 14 | INT | Input | Interrupt request |
| 15 | Ο2 | Input | The second phase of the clock generator signal |
| 16 | INTE | Output | The processor has two commands for setting 0 or 1 level on this pin. The pin normally is supposed to be used for interrupt control. In simple computers, however, it was sometimes used as a single bit output port for various purposes. |
| 17 | DBIN | Output | Read (the processor reads from memory or input port) |
| 18 | WR- | Output | Write (the processor writes to memory or output port). This is an active low output. |
| 19 | SYNC | Output | Active level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide added information to support the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register, e.g., 8238 Wayback Machine-System Controller and Bus Driver. |
| 20 | +5 V | β | The + 5Β V power supply |
| 21 | HLDA | Output | Direct memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus |
| 22 | Ο1 | Input | The first phase of the clock generator signal |
| 23 | READY | Input | Wait. With this signal it is possible to suspend the processor's work. It is also used to support the hardware-based step-by step debugging mode. |
| 24 | WAIT | Output | Wait (indicates that the processor is in the waiting state) |
| 25 | A0 | Output | Address bus |
| 26 | A1 | ||
| 27 | A2 | ||
| 28 | 12 V | β | The +12 V power supply. This must be the last connected and first disconnected power source. |
| 29 | A3 | Output | The address bus; can switch into high impedance state on demand |
| 30 | A4 | ||
| 31 | A5 | ||
| 32 | A6 | ||
| 33 | A7 | ||
| 34 | A8 | ||
| 35 | A9 | ||
| 36 | A15 | ||
| 37 | A12 | ||
| 38 | A13 | ||
| 39 | A14 | ||
| 40 | A11 |
Support chips
The Intel 8080 microprocessor became very successful partly because many supporting chips were available to help it work. These chips helped with tasks like sending information, keeping time, controlling devices, and managing tasks.
The supporting chips included:
- 8214 - Priority Interrupt Control Unit
- 8224 β Clock generator
- 8228/8238 β System controller and bus driver
- (/wiki/Intel_8251) β Communication controller
- (/wiki/Intel_8253) β Programmable interval timer
- (/wiki/Intel_8255) β Programmable peripheral interface
- (/wiki/Intel_8257) β DMA controller
- (/wiki/Intel_8259) β Programmable interrupt controller
Physical implementation
The Intel 8080 microprocessor used a special kind of design called NMOS. This design needed extra power levels, including +12 V and β5 V, in addition to the usual +5 V used in many electronic parts.
It was made using a process called silicon gate, with very tiny details measuring just 6 micrometers. The chip had around 4,500 tiny parts called transistors connected by metal layers. The chip itself was about 20 mmΒ² in size.
Commercial impact
Applications and successors
The 8080 was used in many early computers, such as the MITS Altair 8800, Processor Technology SOL-20, and IMSAI 8080. These machines often ran the CP/M operating system. Later, the Zilog Z80 processor built on this success, becoming very popular along with CP/M from about 1976 to 1983.
Even after newer processors like the Z80 and 8085 came out, the 8080 remained popular. In 1979, five companies were selling about 500,000 units each month for around $3 to $4 each. The 8080 was also used in early single-board computers like MYCRO-1 and in systems for managing money on buses and trains worldwide. It even powered early arcade games, including Gun Fight and Space Invaders.
The 8080 influenced many later processors. Intel followed it with the 8085, and later the 16-bit Intel 8086 and Intel 8088, which IBM used in its first PC. The ideas and instructions from the 8080 live on in todayβs computers.
Industry change
The 8080 changed how computers were made. Before it, big companies like Digital Equipment Corporation, Hewlett-Packard, and IBM built entire computers themselves. The 8080 let anyone create computer systems more easily. For example, Hewlett-Packard used it in smart terminals that could run BASIC, and Microsoftβs first product, Microsoft BASIC, was made for the 8080.
The 8080 helped lead to the creation of the x86 family of processors, which are still used in many computers today. Many of the 8080βs basic ideas and instructions are still part of these modern chips.
US Patent
US patent 4010449, Federico Faggin, Masatoshi Shima, Stanley Mazor, "MOS computer employing a plurality of separate chips", issued March 1, 1977. This patent includes important ideas for early computer design.
Cultural impact
The Intel 8080 chip helped change computers forever, and its influence reached beyond technology. An asteroid in space was named 8080 Intel to honor the chipβs big role in how computers developed. Even some phone numbers, like Microsoftβs 425-882-8080, were picked because they included the numbers from this important chip. Many of Intelβs own phone numbers also used the ending 8080 to remember this key part of their history.
Images
Related articles
This article is a child-friendly adaptation of the Wikipedia article on Intel 8080, available under CC BY-SA 4.0.
Images from Wikimedia Commons. Tap any image to view credits and license.
Safekipedia